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Reply To: sampling phase auto-sync

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#10534

marqs
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Ideally sampling clock and phase would be automatically detected, but in reality I’ve never seen an implementation that would have worked that reliably unless used with static hi-res picture. To get an idea how monitors do auto clock/phase for VGA, I recommend checking this filing.

With TVP7002, a big issue is that you need to use H-PLL post divider with lo-res sources to keep PLL internal frequency high enough – otherwise significant jitter may occur. It wouldn’t be a problem if DIVBY2 was implemented properly, but it seems that divider output is not aligned, so basically you randomly get 0 or 180deg shifted signal every time after locking. One solution could be sampling at 2x rate without DIVBY2, and then handling clock division (dropping every other sample) using FPGA. Alternatively, it might be possible to improve jitter performance by tuning loop filter component values. Both ideas have been on my todo list, but I haven’t had time to look more closely into them yet.