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Reply To: sampling phase auto-sync

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#10669

marqs
Participant

It might be easier to divide incoming pixel clock by 2 as the first thing on FPGA using a basic flip-flop divider, synchronizing latched TVP7002 outputs to this generated output clock. The divider should be made so that output rising/falling clock edge is aligned to latched hsync edge based on user preference, basically giving coarse 0/180deg phase select option (unlike TVP7002 which does it randomly with DIVBY2). With this method you don’t need make changes to PLL settings or actual scanconversion code.

As for FPGA debugging, it’s easy to route (directly or using SignalProbe) sync signals etc. to led/sd pins (as you seem to have done already) and then probing them with scope.