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Generating a divided down clock prior to the PLLs and aligning based on the divided clock is a much simpler solution. I like it. Although, I was unsure whether a flop based clock is safe to use. I gave it a try and got an error:

Error (15065): Clock input port inclk[0] of PLL "scanconverter:scanconverter_inst|pll_3x:pll_linetriple|altpll:altpll_component|pll_3x_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block
	Info (15024): Input port INCLK[0] of node "scanconverter:scanconverter_inst|pll_3x:pll_linetriple|altpll:altpll_component|pll_3x_altpll:auto_generated|pll1" is driven by pclk_05x which is Q output port of Register cell type node pclk_05x

It looks like the Altera PLLs only take an input from a global clock pin or the output of another PLL through a control block. Perhaps there is something I’m missing.

I can use a divided down clock to latch the values inside the scanconverter block and modify the PLLs to provide divide by 2 clocks. That’s still a lot simpler than what I currently have.