My changes are at: https://github.com/RedGuyyyy/ossc/tree/master
Marqs suggested the fix for the sampling phase shift so I’m sure he knows what needs to be done and a cleaner way to do it. My fix is also incomplete. It would be better to move the clock divider for all DIVBY2 resolutions to the FPGA, but when I tried doing that both linex2 and linex3 m0/m1 would occasionally flash a set of black frames. If I can figure out why it would simplify the change.