Home › Forums › OSSC › OSSC – Feature Requests › 1920 lines horizontal sampling/output for all inputs + aspect ratio controls › Reply To: 1920 lines horizontal sampling/output for all inputs + aspect ratio controls
@marqs: Yeah, storing relatively large arrays/.mif:s for mostly similar configurations is not optimal considering current memory limitations.
For Cyclone IV (not III as I previously mentioned, that was the other FPGA on the board), we had 26 bytes for each configuration, though it’s possible that could be optimised. Our NIOS code was stored in external flash (EPCS device IIRC) and ran from DDR, so no such memory limitations for us! For Cyclone V, each configuration requires 6x 32-bit values, so about the same. It probably (also) depends on the number of output clock’s you’re using…
Those design decisions were made by our client, not us (contract design engineers). That particular client was a component distributor and chose most of the silicon for us to use in the design, including the TVP7002. We have it all under NIOS control, so at least it’s trivial for us to tweak the registers.
- This reply was modified 3 weeks, 2 days ago by tcdev.