Of course the hardest part would be programming the firmware and it would most likely need a separate firmware because of the different FPGA but the framebuffer would be an optional feature. It would not replace the zero lag processing of the current hardware.
With the extra RAM and PLL you can also optionally normalize the output with around 1 to 2ms delay. You don’t need to use a full framebuffer for that.
So with that said I fail to see how it would be quite different. What kind of different design considerations do you have in mind?