I’ve noticed a minor bug in timing tweaker so I’ll prepare a small fw update at the end of this week including also the option for MVS sync compatibility.
MVS nominally has 64us hsync period, but for some reason MV1A had 3 cycles during vblank that were 71.2us, 62us and 58.8us. I thought that mode detection logic in the digitizer chip would ignore such variations during vblank (does actually only during vsync), so that led to no stable sync being detected/processed. It was hard to notice such variation from oscilloscope traces of c-sync signal which includes serration pulses etc, but it became quite apparent after running it through ISL59885 that converted c-sync to separate H+V sync. Fortunately there’s a register in the digitizer chip that could be used for increasing detection tolerance and thus fix the issue, so that will be exposed on the fw. Additionally, H-PLL coast parameters must be set to 3 or higher so that PLL does not try to use those hsync edges as reference.