PLL, what is it?

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    There are 3 PLL related settings in the OSSC, can someone please clarify what exactly do they do?
    I assume PLL stands for Phase Locked Loop, but how does it relate to video and sync?

    Allow TVP HPLL2x
    H-PLL Pre-Coast
    H-PLL Post-Coast



    The Wiki has descriptions for those settings here, here, and here; or are you looking for detail beyond what the manual contains?



    Indeed I am.

    Each of the H-PLL functions does something very specific and I am determined to know what exactly it is.



    Additional details can be found in TVP7002 datasheet.



    Thank you.
    So the OSSC is an FPGA controlled TVP7002 which is a brilliant idea. 🙂

    If I understand correctly PLL stabilizes the HSync because HSync is somehow unstable or distorted when VSync is active?;
    and H-PLL pre/post coast are the region in time where the PLL locks/unlocks a more stable HSync signal while the VSync does its job and replaces the unstable HSync with the fixed-HSync while it’s active.
    Please confirm…

    Now that raises few question;
    Why the analog HSync during Vsync so distorted that it requires fixing before digitization?
    Why some consoles require more than other?
    How a CRT handles it?

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